The present invention relates to a non-volatile semiconductor memory device and more particularly to techniques for allowing for high integration and high performance of a non-volatile semiconductor memory device using electrically alterable memory cells each having a two-layered gate structure of a charge storage layer and a control gate layer.
Conventionally there is known a form of electrically erasable programmable read only memory (EEPROM) in which MOS transistor-structured memory cells each having a multilayered structure of a charge storage layer and a control gate layer are arranged in a matrix.
FIG. 11 is a fragmentary plan view of an EEPROM of a NAND cell array in which each NAND cell comprises a plurality of memory cells connected in series. A plurality of signal lines BLj (shown for j=1 to 3; hereinafter referred to as bit lines) and a common line (hereinafter referred to as a source line) are connected to memory cells M(i, j) (shown for i=1 to 16 and j=1 to 3) through bit line contacts and source line contacts, respectively. The source line is connected to a reference voltage (e.g., ground potential).
In each column, memory cells M(1, j) to M(16, j) are series-connected so that adjacent memory cells share a diffused layer serving as a source/drain, thus forming a NAND cell.
The memory cells each have a multilayered gate structure of a charge storage layer (hatched by broken lines in FIG. 11) and a control gate layer for controlling an amount of charge stored in the charge storage layer. The charge storage layer is isolated from adjacent ones between each bit line. The control gate layers of the memory cells in each row are contiguous to be formed into one of word lines WLi (i=1 to 16) that intersect the bit lines BLj (j=1 to 3). Each word line WLi is connected to one memory cell M(i, j) for each bit line BLj.
To selectively write into and read from the memory cells, each NAND cell further comprises two select gate cells S(k, j) (k=1, 2, j=1 to 3) connected to both ends of the series-connected memory cells M(i, j).
That is, the two select gate cells S(k, j) are placed adjacent to the bit line contact and the source line contact. The memory cells M(i, j) and the two select gate cells S(k, j) are formed in each device region that extends in the direction of length of the bit lines Bj so that adjacent ones share a source/drain diffused region. The device regions are isolated by device isolation regions.
The switching control of the select gate cells S(k, j) is performed by two select gate lines SGk (k=1, 2). One of the select gate lines is provided on the bit line side and the other of the select gate lines is provided on the source line side. As an alternative, two or more select gate cells may be placed on each side.
FIG. 12 is a sectional view taken along line XII--XII of FIG. 11.
The memory cell M(i,1) and the select gate cell Sk1 are each formed from a silicon substrate (p-well region) 1, n-type diffused layers la serving as source/drain regions, a first gate insulating layer 4 made of a thin silicon oxide film formed on the substrate, a charge storage layer 5 made of polysilicon, a second gate insulating film 6 formed on the charge storage layer 5 at a thickness larger than the first gate insulating layer, and a control gate layer 7 made of polysilicon.
The charge storage layer 5 in the memory cell M(i, j) is left floating and the tunnel injection of electrons from the n-type channel of the memory cell into the charge storage layer allows the memory cell to be written into. At this point, a write control voltage is applied to the control gate layer 7. The operation of the EEPROM will be described in detail later.
The EEPROM of FIG. 12 further comprises an interlayer insulating film 8, a bit line (BL1) 9, a bit line contact 10, a source line 11, and a source line contact 12. A sectional view taken along line XIII--XIII of FIG. 11 is shown in FIG. 13.
In FIG. 13, like reference numerals are used to denote corresponding parts to those in FIG. 12. WL1 is a word line 13 that is made of a continuous control gate layer 7. The memory cells M(1, j) (j=1 to 3) are isolated by isoplanar-type device isolation regions 3a.
In the cross sectional structure of FIG. 12, the select gate cell Sk1, like the memory cell M(i, j), has a multilayered gate structure of charge storage layer 5 and control gate layer 7. It has been thought heretofore that there is no need of providing a charge storage layer 5 in particular in the select gate cell Sk1 because the select gate cell is no more than a switching transistor used to selectively write data into or read data from the memory cells.
If the select gate cell is formed to have the same gate structure as the memory cell as shown in FIG. 12, then the mask alignment process will become simple in comparison with the case where each of them has a separate structure, which is favorable for high-density integration. For this reason, in many cases the select gate cell is also formed with the charge storage layer as in the case of the memory cell and contact is then made to the charge storage layer.
As an example, a conventional method to make contact to the charge storage layer of the select gate cell on the bit line side is illustrated in FIG. 14. The charge storage layer (FG) indicated by right-downward broken lines (and partially by right-downward continuous lines) and the control gate layer (CG) indicated by left-downward continuous lines indicate the planar shape of the charge storage layer 5 and the control gate 7.
SG1 indicates the select gate on the bit line side and WL1 indicates a word line adjacent to SG1. Vertical dash-dotted lines indicate the boundaries of the device isolation region. Vertical dashed lines on the WL1 indicate the edges of the respective FGs in the device isolation region. The FG portions formed below the CG are indicated by broken lines.
As shown in FIG. 14, in the select gate SG1 a FG is made of a continuous layer over the whole area thereof. A portion of the CG is removed in the device isolation region and the FG in the contact area is broadened in the form of a pad to make contact to the FG. Thus, alignment margin for the contact portion is needed, which prevents high-density integration of EEPROM. On the other hand, as shown by the vertical broken lines on the word lines in FIG. 11, the memory cell charge storage layers 5 associated with adjacent bit lines are isolated from each other in the device isolation region. In the plan view of FIG. 11, vertical broken lines indicating the boundaries of the charge storage layers 5 are not shown in the select gate cells S(k, j) connected to the select gates SG1 and SG2; for, in practice, the continuous charge storage layer is formed as shown in FIG. 14.
In FIG. 11, the contact portion for the charge storage layer and the control gate layer shown in FIG. 14 is omitted. In FIG. 14, the boundaries of the charge storage layers are shown by vertical broken lines on WL1 because they are isolated from each other in the device isolation region.
FIG. 15 is a plan view of a mask pattern used in a lithography process for separating the charge storage layer between each bit line after the deposition of polysilicon as the charge storage layers of the respective memory cells M(i, j). In FIG. 15, M(1, j) (j=1 to 3) and S1j (j=1 to 3) indicate areas where memory cells and select gate cells are to be formed, respectively. WL1 and SG1 are a word line and a select gate, respectively.
It is required to remove a portion of the charge storage layer of the memory cells M(1, j) connected to the word line WL1 between each bit line, but the charge storage layer of the select gate cells S1j connected to the select gate SG1 is left continuous as shown in FIG. 15.
Thus, the mask pattern shown in FIG. 15 will have to be provided, as shown by arrows in FIG. 15, with boundaries between the areas where the charge storage layer is cut into sections and the areas where the charge storage area is not cut. However, such boundaries will make it necessary to make allowance for additional alignment margin in the lithography process in comparison with the case where no boundaries are included. In such a case, it will become very difficult to minimize the spacing between the word line WL1 connected to the memory cells and the select gate SG1 connected to the select gate cells.
Next, explanation is made of the problems with the case where, as shown in FIG. 16, the select gate cells are formed into a single-layer structure of the control gate layer 7 alone so that contact to the charge storage layer can be removed for ease of high-density integration.
FIG. 16 is a sectional view corresponding to FIG. 12. Whereas the memory cells M(i,1) have the multilayered gate structure of the charge storage layer 5 and the control gate layer 7, the select gate cells Sk1 have a single-layer gate structure of the control gate layer 7. To form the single-layer gate structure, either of the two gate layers has to be processed or removed.
As described previously in conjunction with FIG. 15, to remove one of the gate layers of the select gate cells, additional mask alignment is needed in the lithography process and alignment margin has to be allowed for. For this reason, the spacing between the select gate SGk and the word line WLi cannot be made small enough in comparison with the spacing between each word line. This is a serious problem in fine pattern formation of the memory cell array.
Using FIG. 17, explanation is made of problems in the case where the memory cells and the select gate cells each have the multi-layered gate structure and, as with the memory cells, the charge storage layer of the select gate cells is also cut into sections between each bit line. FIG. 17 is a sectional view corresponding to FIG. 11.
Since the charge storage layer 5 of the select gate cells is cut between each bit line, to connect the charge storage layer 5 and the control gate layer 7 the removal of the second gate insulating film 6 between the charge storage layer and the control gate layer is more suitable for improving integration density than the provision of many such contacts as shown in FIG. 14.
However, since the second gate insulating film 6 must be left in the memory cells, the removal of the second gate insulating film only for the select gate cells will need such a mask pattern as shown in FIG. 18.
In FIG. 18, horizontal broken lines indicate the word line WL1 to which the memory cells M(1, j) are connected and the select gate lines SG1 to which the select gate cells S1j are connected. The vertical broken lines on the word line WL1 and the select gate line SG1 indicate the edges of the charge storage layers 5 of the memory cells and the select gate cells.
By removing the second gate insulating film 6 in the regions where the select gate cells are formed using the mask pattern shown in FIG. 18, the charge storage layers of the select gate cells S1j are all connected to the select gate SG1.
However, the mask pattern shown in FIG. 18 will have to be provided, as shown by arrows, with boundaries between the areas where the second gate insulating film is removed and the areas where the gate insulating film is not removed, making it necessary to make allowance for additional alignment margin. In such a case, it will become very difficult to minimize the spacing between the word line WL1 and the select gate SG1.
Increasing the spacing between the select gate SGk and the word line WLi in comparison with the spacing between each word line leads to an increase in the occupied area of the memory cell array and a significant decline in dimensional controllability. This will be explained below.
As is well known, in a fine pattern formation process with a minimum dimension of 0.25 .mu.m or below, when the spacing between pattern elements is widened, the proximity effect becomes marked, resulting in dimensional shrinkage in lithography or dimensional expansion in RIE (reactive ion etching). Thus, the dimensional controllability declines considerably. In the presence of differently spaced pattern elements in the memory cell array, therefore, it becomes very difficult to control the dimensions precisely.
The EEPROM has been expected to find use as a constituent element in a mass storage recording device and it is therefore required that the cell area be minimized and the cost per bit of storage be reduced. To this end, scaling rules are applied to minimize the width (gate length) of and the spacing between gates in the direction of bit line length.
Under such circumstances, the provision of new contact to the charge storage layer 5 of the select gate cells or the addition of a new mask alignment process for producing differently structured memory and select gate cells prevents the fine pattern formation of EEPROM and limits the range of applicability thereof.
The problems in the operation of NAND type EEPROM will be described next. Conventionally, a self-boost writing technique which allows writing into EEPROM at a low voltage has been developed and put into practical use.
The technique allows transistors in a column decoder connected to bit lines and the like to be operated from a Vcc power supply (3.3V), thus resulting in a reduction in the area of peripheral circuitry and consequently in the chip area.
The conventional self-boost write operation will be described with reference to FIG. 19, which illustrates an equivalent circuit of NAND type EEPROM with an operating voltage supplied to each terminal in a self-boost write operation. This equivalent circuit comprises bit lines BL1 and BL2, select gates SG1 and SG2, word lines WL1 to WLn formed of control gate layers of memory cells, and a source line.
Here, an operation of writing two-valued data ("1" or "0") into one memory cell will be described. In the case of multi-valued data, it is simply required that "1" data be changed for "0" data (the threshold voltage is negative) and "0" data be changed for "1", "2", and "3" data (the threshold voltage is positive and each data is defined by a certain threshold voltage range). Even with multi-valued memories with no such threshold voltage distribution, a like operation can be performed as long as different threshold voltages are set.
In FIG. 19, when the word line WL2 is selected to write a 0 into the memory cell A (M(2,1)) in a solid circle placed at the intersection of the bit line BL1 and the word line WL2, erroneous writing may occur in non-selected cells B (M(2,2)) and C (M(3,1)) circled by broken lines.
Note that, in FIG. 19, the non-selected cells B and C are merely shown as an example. The same problem as with the cell B also arises in memory cells connected to the selected word line WL2 and "1" write bit lines other than BL2. The same problem as with the cell C also arises in memory cells connected to the bit line BL1 and non-selected word lines WL1 and WL3 to WLn. In the "1" write state, memory cells are placed in the erase state in which "0" is not written.
Normally, NAND-connected memory cells are sequentially written into starting with the memory cell farthest from the bit line. For random writing, the memory cells are written into at random. In the self-boost write operation, the voltage Vsg2 to the select gate SG2 on the source line side is kept at 0V to place the select gate cells S21 and S22 in the off state.
Next, the voltage VBL1 at the bit line BL1 (selected bit line) connected to the cell A (M(2,1)) into which a 0 is to be written is kept at 0V. To the bit line BL2 (non-selected bit line) connected to the cell B (M(2,2)) into which a 1 is to be written is applied a voltage VBL2 which is equal to voltage Vsg1 to the select gate SG1 on the drain side or a voltage VBL2 which is high or low enough turn the select gate cell S12 off. As a result, the select gate cell S11 is placed in the on state and the select gate cell S12 is placed in the off state. Thus, the bit lines BL1 and BL2 allow memory cells to be selectively written into.
In this state, a transfer voltage Vpass (or a write voltage Vpp) is applied to all the word lines in a selected block comprising a plurality of NAND cells, allowing the memory cells to enter the on state. At a certain value on the rising edge of a voltage pulse, all the memory cells in the selected block are placed in the on state, so that 0V is transferred to the channel of each of the NAND-connected cells connected to the "0" write bit line BL1.
The channel of each of the NAND cells connected to the "1" write bit line BL2 becomes floating with an initial voltage, which is the voltage VBL2 at that bit line minus the threshold voltage of the select gate cell S12, transferred from the bit line BL2 via the select gate S12. At this point, the source line is supplied with 0V or a positive voltage that allows the select gate cells S21 and S22 on the source side to turn off.
Next, when a write voltage pulse Vpp is applied to the selected word line WL2, the cell A connected to that word line and the bit line BL1 supplied with 0V is written with a 0. At this point, the channel of the cell B connected to the selected word line WL2 and the "1" write bit line BL2 is left floating because the select gate cell S12 is cut off.
The channel voltage of the cell B is required to be high enough not to allow a 0 to be written into it. That is, it is required to set the voltage Vch applied to the channel of the cell B so that a variation in the threshold voltage of the cell B due to the write voltage pulse Vpp is within an allowable range. For the cell B, the smaller the difference between the write voltage Vpp and the channel voltage Vch, the smaller the variation in the threshold voltage.
To this end, a certain transfer voltage Vpass is applied to the non-selected word lines WL1 and WL3 to WLn as word line voltages VWL1 and VWL3 to VWLn so as to raise the channel voltage Vch of the cell B to a certain voltage through capacitive coupling. The higher the transfer voltage Vpass, the higher the channel voltage Vch of the cell B. Thus, as Vpass increases in magnitude, the variation in the threshold voltage of the cell B becomes small.
On the other hand, the transfer voltage Vpass is also applied to the non-selected cell C of the memory cells connected to the bit line BL1 supplied with 0V. Unlike the cell B, therefore, the cell C becomes large in the variation in the threshold voltage as Vpass increases in magnitude.
In writing a 0 into the cell A, the threshold voltages of the cells B and C vary in opposite directions with respect to the magnitude of the transfer voltage Vpass. With this in mind, therefore, the optimum value of Vpass should be determined so that variations in the threshold voltage of the cells B and C may both become small. The problem in self-boost writing through capacitive coupling and the problem in determination of the optimum value of Vpass will be described in detail later with reference to FIGS. 20A, 20B, 20C and 22.
Thus, if the transfer voltage Vpass is applied as word line voltages VWL1 and VWL3 to VWLn after the non-selected bit line BL2 has been made floating, the voltage at the channel and the source/drain diffused layer of each of the memory cells connected to the bit line BL2 and the word lines WL1 and WL3 to WLn is boosted through capacitive coupling to correspond with a boost in the transfer voltage Vpass.
FIG. 20A shows equivalent capacitance in the neighborhood of the gate of a memory cell transistor. The equivalent capacitance is given by a series combination of a capacitance C1 and a junction capacitance C2 as shown in FIG. 20B. The capacitance C1 consists of a series combination of a first capacitance formed by the channel, the first insulating film 4, and the charge storage layer 5 (FG) and a second capacitance formed by the charge storage layer 5, the second insulating film 6, and the control gate layer 7 (CG). The capacitance C2 is formed between the source/drain diffused layer 1a and the silicon substrate (p well) 1.
With voltage Vcg (word line voltage of FIG. 19) applied to the control gate layer 7, the channel of the memory cell transistor is supplied with the voltage Vch obtained by capacitive division of Vcg using C1 and C2 as shown in FIG. 20C. Here, C1/(C1+C2) is referred to as the boost ratio of the channel.
With the transfer voltage Vpass being applied as Vcg and the boosted channel voltage Vch having a desired positive value, charge injection into the non-selected cell B connected to the selected word line WL2 common to the selected cell A can be prevented.
Normally, the transfer voltage Vpass and the write voltage Vpp are applied using a step-up system in which their initial voltage, step voltage, final voltage and pulse width are optimized in order to make small a change in the threshold voltage of the cell A and prevent erroneous writing into the cells B and C.
Data written into the memory cells are erased by a simultaneous (at-one-time) erasing technique of erasing data in all the memory cells at one time or a block erasing technique of erasing data on a byte by byte basis.
For at-one-time erase, all the word lines are set to 0V, and a high voltage of, say, 20V is applied to the P well. This allows electrons to tunnel back from the charge storage layers of the memory cells to the P well, shifting the threshold voltage in the negative direction.
For block erase, all the word lines in a selected block are kept at 0V, all the bit lines, the source line, and the word lines in non-selected blocks are placed in the floating state, and a high voltage of, say, 20V is applied to the P well.
For data readout, a read voltage of, say, 4.5V is applied to the select gate and the non-selected word lines connected to non-selected memory cells to thereby turn them on, and the word line connected to the selected cell is kept at 0V. At this point, a current flows on the bit line side. By sensing a variation in the bit line voltage resulting from that current, either a 0 or a 1 is detected.
In the conventional self-boost writing NAND type EEPROM, the following problems have arisen in connection with the structure and manufacturing process of memory cells and the channel voltage applied to the channels of the NAND cells associated with non-selected bit lines. These problems will be described with reference to FIGS. 21 and 22.
FIG. 21 is a timing waveform diagram for use in explanation of the self-boost write operation. When the voltage VBL1 at the "0" write bit line BL1 is set at 0 V, the voltage VBL2 at the "1" write bit line BL2 is set at Vcc (say, 3.3V), and the voltage Vsg1 at the control gate SG1 on the bit line side is set at Vcc, the channels and the diffused layers of NAND cells associated with the bit line BL2 become floating.
After this, when Vpp is applied as the selected word line voltage VWL2 and Vpass as the non-selected word line voltages VWL1 and VWL3 to VWLn, the channels which have been placed in the floating state are boosted to a certain voltage Vch. At this point, the channel voltage Vch is given by EQU Vch=Vsg-Vsgth (Vchinit)+Cr1 .times.(Vpass-Vpassth-Vchinit)+Cr2 .times.(Vpp-Vpassth-Vchinit) -(Tpw/16 (Cins+Cch)).times.I (1)
where Vsg corresponds to Vsg1 in FIG. 19 (for example, Vcc), Vsgth is the threshold voltage of the select gate cell S12 on the drain side when the channel voltage is Vchinit, Cr1 is the boost ratio of the memory cell channel when transfer voltage Vpass is applied, Cr2 is the boost ratio of the memory cell channel when write voltage pulse Vpp is applied, Vpassth is the voltage required to allow the memory cell supplied with transfer voltage Vpass to turn on when the channel voltage is Vchinit, Tpw is the pulse width of write voltage pulse Vpp, Cins is the capacitance per memory cell, Cch is the capacitance of the depletion layer below the channel, and I is the current flowing from the channel to the well and the adjacent bit line.
That is, as shown in the lower portion of FIG. 21, applying the write voltage Vpp to the selected word line WL2 as VWL2 and applying the transfer voltage Vpass to the non-selected word lines WL1 to WL3 to WLn as VWL1 and VWL3 to VWLn allows the channel voltage of the non-selected memory cells in the floating state to be boosted, preventing erroneous cell writing.
Changes in various process conditions, such as the impurity profile of the select gate cells, memory cells and semiconductor substrate (P well), the impurity profile of the cell channels through impurity implantation, the impurity profile of source/diffused layers of the cells and so on may result in the initial voltage Vchinit to the channels being lowered, the channel boost ratios being decreased due to an increase in the depletion capacitance or 0-V terminal-to-channel capacitance. In such case, a sufficiently high channel voltage Vch is not be obtained and the threshold voltage of memory cells connected to non-selected bit lines changes to cause erroneous cell writing.
A relationship between the transfer voltage Vpass and the threshold voltage of the cell B of FIG. 19 into which a 1 is to be written is illustrated by a solid line in FIG. 22. That is, writing into the cell A in the state where Vpass is low causes the threshold voltage of the cell B which was originally Vth1 for "0" writing to increase rapidly and exceed the boundary value between threshold voltages for "1" and "0" writing indicated by a dash-dotted line, which results in erroneous writing into the cell B. If, however, Vpass is set high enough, the channel voltage of the cell B is boosted and its threshold voltage Vth1 is therefore lowered again to Vthl, whereby erroneous writing is prevented.
With the cell C of FIG. 19, since 0V is transferred to its channel as described previously, setting Vpass applied to its control gate high causes the threshold voltage to increase as shown dashed in FIG. 22, resulting in erroneous cell writing. In order to prevent erroneous writing into all the non-selected memory cells, therefore, it is required that the range of Vpass be selected so that both the solid line and the broken line of FIG. 22 lie below the dash-dotted line.
A change in the threshold voltage tends to increase with increasing variations in the gate length and wing width of the memory cells (see FIG. 13), the tunnel oxide film, the inter-poly insulating film (the second gate insulating film 6) and is apt to take place particularly when a great number of bits is contained in a write selected block.
In addition, the greater the leakage current between the well and the floating channel or source/diffused layer, the greater the threshold voltage changes. Variations in characteristics of the select gate cells that transfer the bit line voltage to the channels also have a great influence on the threshold voltage. A change in the threshold voltage will further increase if the short-channel effect becomes less and less negligible as the fine pattern technology progresses further.
Thus, it has been made clear that the characteristics of memory cells and select gate cells associated with the structure and manufacturing process thereof affect the erroneous writing characteristic shown in FIG. 22. For improved performance, improvements in process, structure and operation are required.
From such a viewpoint, a local self boost (LSB) writing technique has been proposed conventionally. In FIG. 23, there is illustrated exemplary voltages applied to individual terminals in an LSB operation. In the LSB operation, 0 V is applied to the non-selected word lines WL1 and WL3 on opposite sides of the selected word line WL2 and Vpass is applied to the other non-selected word lines WL4 to WLn. The non-selected cell M(2,2) and so on that share the word line WL2 with the selected cell M(2,1) are cut off by the back-gate bias effect of the Vpass-boosted channel.
At this point, applying the write voltage Vpp to the selected cell M(2,1) allows the channel of the cell M(2,2) to be boosted in potential due to coupling between the channel capacitance and the source/drain diffusion capacitance of the cell M(2,2).
The resulting channel voltage of the cell M(2,2) is in the range of 8 to 9 V under the condition that Vpp is 18V and the channel boost ratio is 0.5 and serves as a write inhibit voltage. The LSB operation is promising for a method for writing into multi-valued memories but the following problems are involved:
That is, in the LSB operation, the non-selected memory cells M(2,2) and so on that share the word line WL2 with the selected memory cell M(2,1) must be in the cut-off state. In order for the non-selected cells M(2,2) and so on in the erase state to be cut off due to the channel back-gate bias effect, it is required that Vpass be high enough or the threshold voltage be low and negative.
However, with increasing Vpass, the threshold voltage of the memory cells M(4,1) to M(n,1) connected to the non-selected word lines WL4 to WLn cannot be kept from changing. In addition, it is very difficult to make the range over which the threshold voltage in the erase state is distributed small in view of restrictions on the operating time.
As described above, for the self-boost or LSB operation of NAND type EEPROM, the most desirable is to allow the memory cells and the select gate cells to have the common basic structure, to set the impurity profile of the channels and source/drain diffused layers of the memory cells so that a great channel boost ratio results, and to obtain a channel voltage high enough to ensure that erroneous writing into non-selected memory cells is prevented.
By making the channel voltage high, erroneous cell writing can be prevented even with a multi-valued memory in which the write voltage Vpp and the threshold voltage of non-selected cells are high. However, with 0.25 .mu.m or less NAND type memories (the feature size of 0.25 .mu.m or less) in particular, it is difficult to make the channel voltage high enough for the following reasons:
As described above in conjunction with FIGS. 12 and 14, the select gate cells of the conventional NAND type EEPROM have a two-layer gate structure of charge storage and control gate layers as with the memory cells and are used as select gates by making contact to the charge storage layer.
The select gate cells serve two functions of placing non-selected blocks in the cut-off state at read time and placing memory cells connected to non-selected bit lines in the floating state at write time.
The ion implantation conditions for the channels and source/drain diffused layers of the select gate cells and the impurity concentration of the well are set so as to serve the functions. With the progress of fine-pattern technology, it is desired to perform ion implantation into the channels and source/drain diffused layers of the select gate cells and the memory cells at the same time in the same process.
If, therefore, the ion implantation conditions for the channels and source/drain diffused layers of the select gate cells are set so as to serve their two functions, then the capacitances associated with the channel and source/diffused layers of each of the memory cells will increase. This results in the channel boost ratio being lowered and consequently in a failure to obtain a high channel voltage.
A key factor in self-boost and LSB operation is the channel boosting capability of the memory cells. Besides, in connection with the cut-off characteristic, it is also one of the important characteristics that the drain breakdown voltage is high.
In boosting the memory cell channel potential, the transfer voltage Vpass of the order of, say, 8V is applied to the select gate cell drain. At this point, punch-through takes place between the source and drain of the select gate cell. With an insufficient cut-off characteristic, an insufficient rise occurs in the memory cell channel potential simultaneously with the punch-through, resulting in erroneous cell writing.
The punch-through refers to the phenomenon in which the channel length shrinks, the drain depletion layer reaches the source diffused layer, and uncontrollable drain current flows to the source.
Therefore, it is required to avoid the punch-through and enhance the cut-off characteristic of the select gate cell satisfactorily. In general, in order to avoid the punch-through and enhance the cut-off characteristic of the select gate cell, it is effective to increase the impurity concentration below the channel and control the spread of depletion layer from the drain junction. Increasing the impurity concentration below the channel results in an increase in the threshold voltage.
With the gate length reduced as a result of the progress of fine structures of cells, to enhance the cut-off characteristic, it is required to perform ion implantation into the channel region at a higher dose. This results in a further reduction in the channel boost ratio, making it easy for erroneous cell writing to occur. In addition, with the progress of fine structures of cells, the short-channel effect increases variations in writing characteristic, which is a cause of increased erroneous cell writing.
With such ion implantation as meets the cut-off characteristic requirements of the select gate cell, the initial voltage transferred from the source or bit line through the select gate cell to the memory cell channel will be lowered, further lowering the channel voltage.
The ion implantation the conditions of which have been set based on the cut-off characteristic of the select gate cell into the memory cells causes their neutral threshold voltage to increase, resulting in read disturb. The read disturb refers to the change of the threshold voltage for a 1 of write data at data read time.
At this point, the writing characteristic of the memory cells is increased unnecessarily. This results in a great change in the threshold voltage of the memory cells supplied with the transfer voltage Vpass at write time. These problems are common to the self-boost writing and the LSB writing in NAND type EEPROM.
Thus, to enhance the cut-off characteristic of the select gate cell, the impurity concentration below the gate is required to be high and, to increase the channel boosting capability of the memory cells, the impurity concentration below the gate is required to be low. Heretofore, it has been impossible to optimize the characteristics of select gate cells and memory cells at the same time without performing ion implantation separately for each of the different types of cells. As described previously, separate ion implantation steps require additional mask alignment, offering a problem in high-density integration.
As described above, with the conventional EEPROM, the memory cells and the select gate cells are made different in gate structure, which constitutes a serious obstacle to achievement of higher integration density of EEPROM. In connection with this, the memory cells and the select gate cells have to be optimized in their impurity profile, gate oxide thickness, neutral threshold voltage and so on by the use of separate manufacturing processes.